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3.3V 1:9 HIGH-PERFORMANCE, LOW-VOLTAGE BUS CLOCK DRIVER
FEATURES
s 3.3V core supply, 1.8V output supply for reduced s s s s s s s
ClockWorksTM SY89809L
DESCRIPTION
The SY89809L is a High-Performance Bus Clock Driver with 9 differential HSTL (High-Speed Transceiver Logic) output pairs. The part is designed for use in low-voltage (3.3V/1.8V) applications which require a large number of outputs to drive precisely aligned, ultralow skew signals to their destination. The input is multiplexed from either HSTL or LVPECL (Low-Voltage Positive-Emitter-Coupled Logic) by the CLK_SEL pin. The Output Enable (OE) is synchronous so that the outputs will only be enabled/ disabled when they are already in the LOW state. This avoids any chance of generating a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control. The SY89809L features low pin-to-pin skew (50ps max.) and low part-to-part skew (200ps max.)--performance previously unachievable in a standard product having such a high number of outputs. The SY89809L is available in a single space saving package, enabling a lower overall cost solution.
power LVPECL and HSTL inputs 9 differential HSTL (low-voltage swing) output pairs HSTL outputs drive 50 to ground with no offset voltage 500MHz maximum clock frequency Low part-to-part skew (200ps max.) Low pin-to-pin skew (50ps max.) Available in 32-pin TQFP package
PIN CONFIGURATION
VCCO VCCO Q0
Q2
Q0
VCCI HSTL_CLK HSTL_CLK CLK_SEL LVPECL_CLK LVPECL_CLK GND OE
1 2 3 4 5 6 7 8
32 31 30 29 28 27 26 25 24 23 22
Q1
Q2
Q1
VCCO Q3 Q3 Q4 Q4 Q5 Q5 VCCO
Top View TQFP T32-1
APPLICATIONS
s High-performance PCs s Workstations s Parallel processor-based systems s Other high-performance computing s Communications
21 20 19 18
17 9 10 11 12 13 14 15 16
VCCO
PIN NAMES
Pin HSTL_CLK, /HSTL_CLK LVPECL_CLK, /LVPECL_CLK CLK_SEL OE Q0-Q8, /Q0-/Q8 GND VCCI VCCO Function Differential HSTL Inputs
VCCO
Q8
Q8
Q7
Q7
Q6
Q6
LOGIC SYMBOL
CLK_SEL HSTL_CLK
Differential LVPECL Inputs Input CLK Select (LVTTL) Output Enable (LVTTL) Differential HSTL Outputs Ground VCC Core VCC Output
HSTL_CLK
0 9 9 Q0 - Q8 Q0 - Q8
LVPECL_CLK 1 LVPECL_CLK
LEN Q
OE
D
Rev.: A
Amendment: /0
1
Issue Date: March 2000
Micrel
ClockWorksTM SY89809L
TRUTH TABLE
OE(1) 0 0 1 1 CLK_SEL 0 1 0 1 Q0 - Q8 LOW LOW HSTL_CLK LVPECL_CLK /Q0 - /Q8 HIGH HIGH /HSTL_CLK /LVPECL_CLK
SIGNAL GROUPS
Level HSTL HSTL LVPECL LVCMOS/LVTTL Direction Input Output Input Input Signal HSTL_CLK, /HSTL_CLK Q0 - Q8, /Q0 - /Q8 LVPECL_CLK, /LVPECL_CLK CLK_SEL, OE
NOTE: 1. The OE (output enable) signal is synchronized with the low level of the HSTL_CLK and LVPECL_CLK signal.
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VCCI, VCCO VIN IOUT Tstore Rating VCC Pin Potential to Ground Pin Input Voltage DC Output Current (Output HIGH) Storage Temperature Value -0.5 to +4.0 -0.5 to VCCI -50 -65 to +150 Unit V V mA C
NOTE: 1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data book. Exposure to ABSOLUTE MAXIMUM RATING conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Power Supply
TA = 0C Symbol VCCI VCCO ICCI VCC Core VCC Output ICC Core Parameter Min. 3.0 1.6 -- Typ. 3.3 1.8 115 Max. 3.6 2.0 140 Min. 3.0 1.6 -- TA = +25C Typ. 3.3 1.8 115 Max. 3.6 2.0 140 Min. 3.0 1.6 -- TA = +70C Typ. 3.3 1.8 115 Max. 3.6 2.0 140 Unit V V mA
HSTL
TA = 0C Symbol VOH VOL VIH VIL VX IIH IIL Parameter Output HIGH Output LOW Voltage(1) Voltage(1) Min. 1.0 0 VX +0.1 -0.3 0.68 +20 -- Typ. -- -- -- -- -- -- -- Max. 1.2 0.4 1.6 VX -0.1 0.9 -350 -500 Min. 1.0 0 VX +0.1 -0.3 0.68 +20 -- TA = +25C Typ. -- -- -- -- -- -- -- Max. 1.2 0.4 1.6 VX -0.1 0.9 -350 -500 Min. 1.0 0 VX +0.1 -0.3 0.68 +20 -- TA = +70C Typ. -- -- -- -- -- -- -- Max. 1.2 0.4 1.6 VX -0.1 0.9 -350 -500 Unit V V V V V A A
Input HIGH Voltage Input LOW Voltage Input Crossover Voltage Input HIGH Current Input LOW Current
NOTE: 1. Outputs loaded with 50 to ground.
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Micrel
ClockWorksTM SY89809L
DC ELECTRICAL CHARACTERISTICS
LVPECL
TA = 0C Symbol VIH VIL IIH IIL Parameter Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current Min. Max. TA = +25C Min. Max. TA = +70C Min. Max. Unit V V A A
VCCI - 1.165 VCCI - 0.880 VCCI - 1.165 VCCI - 0.880 VCCI - 1.165 VCCI - 0.880 VCCI - 1.810 VCCI - 1.475 VCCI - 1.810 VCCI - 1.475 VCCI - 1.810 VCCI - 1.475 -- 0.5 +150 -- -- 0.5 +150 -- -- 0.5 +150 --
LVCMOS/LVTTL
TA = 0C Symbol VIH VIL IIH IIL Parameter Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current Min. 2.0 -- +20 -- Typ. -- -- -- -- Max. -- 0.8 -250 -600 Min. 2.0 -- +20 -- TA = +25C Typ. -- -- -- -- Max. -- 0.8 -250 -600 Min. 2.0 -- +20 -- TA = +70C Typ. -- -- -- -- Max. -- 0.8 -250 -600 Unit V V A A
AC ELECTRICAL CHARACTERISTICS(1)
TA = 0C Symbol tPHL tPLH fMAX tskew tskpp VPP VCMR tS tH tr tf Parameter Propagation Delay(2) Min. -- 500 -- -- 600 -1.5 1.0 0.5 300 Typ. 1.0 -- -- -- -- -- -- -- -- Max. -- -- 50 200 -- -0.4 -- -- 800 Min. -- 500 -- -- 600 -1.5 1.0 0.5 300 TA = +25C Typ. 1.0 -- -- -- -- -- -- -- -- Max. -- -- 50 200 -- -0.4 -- -- 800 -- 500 -- -- 600 -1.5 1.0 0.5 300 TA = +70C Min. Typ. 1.0 -- -- -- -- -- -- -- -- Max. -- -- 50 200 -- -0.4 -- -- 800 Unit ns MHz ps ps mV V ns ns ps
Maximum Operating Freq.(3) Within-Device Part-to-Part Skew(4) Swing(6) Skew(5)
Minimum Input LVPECL_CLK
Common Mode Range(7) LVPECL_CLK OE Set-Up Time(8) OE Hold Time Output Rise/Fall Time (20% - 80%)
NOTES: 1. Outputs loaded with 50 to ground. Airflow 300 LFPM. 2. Differential propagation delay is defined as the delay from the crossing point of the differential input signals to the crossing point of the differential output signals. 3. Output swing greater than 450mV. 4. The within-device skew is defined as the worst case difference between any two similar delay paths within a single device operating at the same voltage and temperature. 5. The part-to-part skew is defined as the absolute worst case difference between any two delay paths on any two devices operating at the same voltage and temperature. 6. The VPP (min.) is defined as the minimum input differential voltage which will cause no increase in the propagation delay. 7. VCMR is defined as the range within which the VIH level may vary, with the device still meeting the propagation delay specification. The numbers in the table are referenced to VCCI. The VIL level must be such that the peakto-peak voltage is less than 1.0V and greater than or equal to VPP PRODUCT ORDERING CODE (min.). The lower end of the CMR range varies 1:1 with VCCI. The VCMR (min) will be fixed at 3.3V - |VCMR (min)|. 8. OE set-up time is defined with respect to the rising edge of the clock. Ordering Package Operating OE HIGH-to-LOW transition ensures outputs remain disabled during Code Type Range the next clock cycle. OE LOW-to-HIGH transition enables normal SY89809LTC T32-1 Commercial operation of the next input clock.
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Micrel
ClockWorksTM SY89809L
32 LEAD TQFP (T32-1)
MICREL-SYNERGY
TEL
3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA
FAX
+ 1 (408) 980-9191
+ 1 (408) 914-7878
WEB
http://www.micrel.com
This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc. (c) 2000 Micrel Incorporated
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